/* The following sets up an array called siop_reg that provides easy access
 * to the c8xx's registers.  Once siop_reg is set to the address of the chip,
 * all registers can be accessed by their name. */

#define SIOP_SEGMENT_ADDRESS 0xd800
#define SIOP_OFFSET_ADDRESS  0x7e00

enum regs {
    SCNTL0 = 0x00,
    SCNTL1 = 0x01,
    SCNTL2 = 0x02,
    SCNTL3 = 0x03,
    SCID = 0x04,
    SXFER = 0x05,
    SDID = 0x06,
    GPREG = 0x07,
    SFBR = 0x08,
    SOCL = 0x09,
    SSID = 0x0a,
    SBCL = 0x0b,
    DSTAT = 0x0c,
    SSTAT0 = 0x0d,
    SSTAT1 = 0x0e,
    SSTAT2 = 0x0f,
    DSA = 0x10,
    ISTAT = 0x14,
    CTEST0 = 0x18,
    CTEST1 = 0x19,
    CTEST2 = 0x1a, 
    CTEST3 = 0x1b,
    TEMP = 0x1c,
    DFIFO = 0x20,
    CTEST4 = 0x21,
    CTEST5 = 0x22,
    CTEST6 = 0x23,
    DBC = 0x24,
    DCMD = 0x27,
    DNAD = 0x28,
    DSP = 0x2c,
    DSPS = 0x30,
    SCRATCHA = 0x34,
    DMODE = 0x38,
    DIEN = 0x039,
    DWT = 0x3a,
    DCNTL = 0x3b,
    ADDER = 0x3c,
    SIEN0 = 0x40,
    SIEN1 = 0x41,
    SIST0 = 0x42,
    SIST1 = 0x43,
    SLPAR = 0x44,
    SWIDE = 0x45,
    MACNTL = 0x46,
    GPCNTL = 0x47,
    STIME0 = 0x48,
    STIME1 = 0x49,
    RESPID0 = 0x4a,
    RESPID1 = 0x4b,
    STEST0 = 0x4c,
    STEST1 = 0x4d,
    STEST2 = 0x4e,
    STEST3 = 0x4f,
    SIDL = 0x50,
    SODL = 0x54,
    SBDL = 0x58,
    SCRATCHB = 0x5c
};

extern volatile ubyte far *siop_reg;