PYXIS Memory Error Status Register (MEAR)

Address: 87.4000.8440 The command, memory sequencer state, the data cycle at the time of an error, and the remaining address field are locked into the MESR register upon a PYXIS error. The error bits are write one to clear and clearing all error bits in the PYXIS_ERR register unlocks this register. When the register is not locked, the contents of this register are not defined.
SEQ_STATE	<31:25>RW	The memory sequencer-state when the nonexistent memory error occurred.
DATA_CYCLE _TYPE	<24:20>RO	The type of data cycle in progress when an ECC error occurred.
Reserved	<19:18>RO	N/A
OWORD_ INDEX	<17:16>RO	The data cycle within a memory access in which the data error was discovered. There are normally four data cycles. OWORD_INDEX = 0 is the first data cycle corresponding to the error address captured in the ERROR_ADDR field. The actual low-order bits of the error location are (ERROR_ADDR[5:4]+ OWORD_INDEX) mod 4.
TLBFILL_NXM	<15>RO	Nonexistent memory trap during a scatter/gather translation buffer fill operation.
VICTIM_NXM	<14>RO	Nonexistent memory trap during a BCACHE victim operation.
IO_WR_NXM	<13>RO	Nonexistent memory trap during an I/O write.
IO_RD_NXM	<12>RO	Nonexistent memory trap during an I/O read.
CPU_WR_NXM	<11>RO	Nonexistent memory trap during a CPU write.
CPU_RD_NXM	<10>RO	Nonexistent memory trap during a CPU read.
DMA_WR_NXM	<9>RO	Nonexistent memory trap during a DMA write.
DMA_RD_NXM	<8>RO	Nonexistent memory trap during a DMA read.
ERROR_ADDR <39:32>	<7:0>RO	Contains address bits <39:32> of the error address in the Memory port when the PYXIS detects an error. Bits <39:34> are unpredictable on memory errors. Only bits <33:32> are are valid for that case.

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DataCycle Type Encodings
(Return to bit descriptions.)

DATA_ CYCLE_ TYPE	Description
00	IDLE
01	CPU_READ
02	CPU_READ_VICTIM
03	CPU_WRITE
04	IO_READ
05	FLASH_BYTE_READ
06	PCI_READ
07	IO_WRITE
08	FLASH_BYTE_WRITE
09	DMA_READ
0A	DMA_READ_SCACHE
0B	DMA_READ_BCACHE
0C	DMA_READ_VICTIM
0D	DMA_WRITE
0E	DMA_MEM_MERGE
0F	DMA_SCACHE_MERGE
10	DMA_BCACHE_MERGE
11	DMA_VICTIM_MERGE
12	FLASH_READ
13	VICTIM_WRITE
14	DUMMY_READ
15	VICTIM_EJECT

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Memory Sequencer State Encodings
(Return to bit descriptions.)

SEQ_STATE	Value	Description
IDLE	00	Command dispatch
WAIT	01	Wait until data transfer is idle
WAIT1	02	Wait one cycle
DMA_RD_START	03	Select DMA read address
DMA_RD_PROBE	04	Assert RAS
DMA_RD_SCACHE_DATA	05	Read Dirty data from Bcache
DMA_RD_BCACHE_DATA	06	Read Dirty data from Bcache
DMA_RD_CACHE_DATA	07	Read Dirty data from Bcache or Scache
DMA_RD_RAS	08	Continue to assert RAS after cache miss
DMA_RD_COL	09	wait for column access
DMA_RD_VICTIM	0A	wait for memory data to blow by
DMA_RD_NXM	0B	Assert error state for nonexistent memory
DMA_WR_START	0C	Select DMA write address
DMA_WR_WHOLE_RAS	0D	Start RAS for whole cache line write
DMA_WR_WHOLE_DATA	0E	Watch the data go by
DMA_WR_PROBE	0F	wait for probe result
DMA_WR_SCACHE_COPY	10	Read Dirty data from Scache
DMA_WR_BCACHE_COPY	11	Read Dirty data from Bcache
DMA_WR_CACHE_COPY	12	Read Dirty data from Bcache or Scache
DMA_WR_RAS	13	Continue to assert RAS after miss
DMA_WR_PQ_RD_RAS	14	Assert RAS for partial octawords read
DMA_WR_PQ_RD_COL	15	wait for column access
DMA_WR_PQ_RD_VICTIM	16	wait for memory data to blow by
DMA_WR_NXM	17	Assert error state for nonexistent memory
DMA_WR_WHOLE_RASF	36	Start RAS for whole cache line write, BC flush pending
DMA_WR_WHOLE_FLUSH	37	Watch the data go by
CPU_EJECT	18	Eject victim and assert RAS for fill
CPU_RD_START	19	Assert RAS for fill
CPU_RD_COL	1A	wait for column access
CPU_RD_VICTIM	1B	wait for DRAM data to blow by, then provide the REAL data
CPU_RD_NXM	1C	Assert error state for nonexistent memory
CPU_WR_START	1D	Assert RAS for Scache victim (no Bcache)
CPU_WR_NXM	1E	Assert error state for nonexistent memory
VICTIM_START	1F	Assert RAS for Bcache victim in Pyxis victim buffer
VICTIM_NXM	20	Assert error state for nonexistent memory
REFRESH_PRECHARGE	21	Deactivate all rows for refresh
REFRESH_COMMAND	22	Assert refresh for all banks
MODE_PRECHARGE	23	Deactivate all rows for "Mode" cycle
MODE_COMMAND	24	Assert Mode cycle for all banks, join refresh flow
CPU_IO_RD_ADDR	25	Send IO read address to select a target
CPU_IO_RD_WAIT	26	Wait for return of read data (64-bit max)
CPU_IO_RD_START	27	Start read data transfer
CPU_FLASH_RD_WAIT	28	wait for flash byte read to complete
UNREACHABLE_STATE	29	****** This state is not reachable ******
CPU_PCI_RD_WAIT	2A	Wait for BC IDLE
CPU_PCI_RD_START	2B	delay for data cycle
CPU_IO_WR_ADDR	2C	Send I/O write address to select a target
CPU_IO_WR_NXM	2D	Assert error state for nonexistent I/O address
CPU_FLASH_WR_WAIT	2E	wait for flash byte write to complete
CPU_FLASH_START	2F	Start a fill from flashROM
CPU_FLASH_COL	30	Start a fill from flashROM
CPU_FLASH_DATA	31	Wait for the Flash controller to deliver all the Flash data
CPU_DUMMY_START	32	Start a fill from the dummy region
CPU_DUMMY_COL	33	Start the dummy data transfer
NO_BRAINER	34	issue CACK and ignore
BAD_CPU_CMD	35	assert machine check

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