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Address: 87.4000.8400 The low-order address bits of the Memory Port Address bus are locked into this register when a PYXIS-detected error occurs. The contents are read only. Clearing all the error bits in the PYXIS_ERR register unlocks this register. When the register is not locked, the contents of this register are not defined. | ||
| ERROR_ADDR<31:4> | <31:4>RO | Contains the current address in the Memory Port when the PYXIS detects an error. |
| Reserved | <3:0>RO | N/A |