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Address: 87.4000.8200 The PYXIS_ERR register is used to log information pertaining to an error condition detected in the PYXIS chip. All bits of the PYXIS_ERR, except the LOST bits will be locked until the PYXIS_ERR is cleared by a software write. The LOST bits will be set whenever the PYXIS_ERR is already locked and another error is detected. | ||
| ERR_VALID | <31>RO | An error has been detected, and the PYXIS_ERR CSR is locked. |
| Reserved | <30:28>RO | N/A |
| LOST_IOA _TIMEOUT | <27>RO | While PYXIS_ERR CSR was locked, an I/O timeout occurred. An I/O read/write failed to be executed in 1 second. |
| Reserved | <26>RO | N/A |
| LOST_PA _PTE_INV | <25>RO | While PYXIS_ERR CSR was locked, an invalid Page Table entry on Scatter/Gather access occurred. |
| LOST_RCVD _TAR_ABT | <24>RO | While PYXIS_ERR CSR was locked, the PCI master state machine received a target abort. |
| LOST_RCVD _MAS_ABT | <23>RO | While PYXIS ERR CSR was locked, the PCI master state machine generated a Master Abort. |
| LOST_PCI _ADDR_PE | <22>RO | While PYXIS_ERR CSR was locked, a PCI Address Parity error was detected. |
| LOST_PERR | <21>RO | While PYXIS_ERR CSR was locked, a PCI Data Parity error was detected. |
| Reserved | <20>RO | N/A |
| LOST_MEM _NEM | <19>RO | While PYXIS_ERR CSR was locked, an access to nonexistent memory was detected. |
| LOST _CPU_PE | <18>RO | While PYXIS_ERR CSR was locked, a CPU parity error was detected. |
| LOST_UN _COR_ERR | <17>RO | While PYXIS_ERR CSR was locked, an uncorrectable ECC error was detected. |
| LOST_COR _ERR | <16>RO | While PYXIS_ERR CSR was locked, a correctable ECC error was detected. |
| Reserved | <15:12;>RO | N/A |
| IOA _TIMEOUT | <11>RW1C | I/O time-out occurred. I/O read/write failed to be executed in 1 second. |
| Reserved | <10>RO | N/A |
| PA _PTE_INV | <9>RW1C | Invalid Page Table entry on Scatter/Gather access. |
| RCVD _TAR_ABT | <8>RW1C | PCI master state machine received target abort. |
| RCVD _MAS_ABT | <7>RW1C | PCI master state machine generated master abort. |
| PCI _ADDR_PE | <6>RW1C | PCI bus Address Parity error detected. |
| PCI_PERR | <5>RW1C | PCI bus Data Parity error detected. |
| PCI_SERR | <4>RW1C | PCI bus SERR detected. |
| MEM_NEM | <3>RW1C | Access to nonexistent memory detected. |
| CPU_PE | <2>RW1C | EV56 bus parity error detected. |
| UN_COR _ERR | <1>RW1C | Uncorrectable ECC error detected. This error cannot occur for a CPU to memory read/write (CPU/mem read ECC errors are detected by the EV56. CPU/mem writes are not checked). This error is applicable to a DMA, a S/G TLB miss, or an I/O write from the EV56. |
| COR_ERR | <0>RW1C | Correctable (single bit) ECC error detected. This error cannot occur for a CPU to memory read/write (CPU/mem read ECC errors are detected by the EV56; CPU/mem writes are not checked). This error is applicable to a DMA, S/G TLB miss, or an I/O write from the EV56. |