Diagnostic Control Register Bit Descriptions

Address: 87.4000.2000
The PYXIS force error register is a diagnostic/debug register to allow various errors to be tested.

FPE_TO_EV56

<31>RW

When FPE_CPU_EV56 is set, a parity error is forced on the CPU address/CMD bus when the PYXIS is the bus master.

Reserved

<30>RO

N/A

FPE_PCI

<29:28>RW

00	Normal Parity is output to the PCI.
01	Bad parity is forced onto the low 32 bits of the PCI during data cycles.
10	Bad parity is forced onto the high 32 bits of the PCI during data cycles.
11	Bad parity is forced onto the high and low 32 bits to the PCI during address and data cycles.

Reserved

<27:2>RO

N/A

USE_CHECK

<1>RW

When set, DMA write cycles and PCI I/O read cycles use the value in the DIAG_CHECK register for ECC sent on the IOD Bus.

Reserved

<0>RW

N/A