| Address: IPR Ibox, Index=100 The interrupt summary register is a read-only register that provides a record of all currently outstanding hardware, software, and asynchronous system trap (AST) interrupt requests and summary bits at the time of a read. | ||
| HLT | <34>R | External hardware interrupt - halt. |
| SLI | <33>R | Serial line interrupt request. |
| CRD | <32>R | Correctable read error interrupt request. |
| MCK | <31>R | External hardware interrupt--system machine check. |
| PFL | <30>R | External hardware interrupt - power fail. |
| PC2 | <29>R | Performance counter 2 interrupt request. |
| PC1 | <28>R | Performance counter 1 interrupt request. |
| PC0 | <27>R | Performance counter 0 interrupt request. |
| I23 | <23>R | External hardware interrupt - irq_h<3> |
| I22 | <22>R | External hardware interrupt - irq_h<2>. |
| I21 | <21>R | External hardware interrupt - irq_h<1>. |
| I20 | <20>R | External hardware interrupt - irq_h<0>. |
| ATR | <19>R | This bit is set if any AST request and corresponding enable is set. This bit also requires that the processor mode is equal to or higher than the request mode. |
| SIRR<15:01> | <18:04> | Corresponds to software interrupt requests 15 to 1. |
| ASTER and ASTRR | <03:00> | Boolean AND of ASTRR |