| Address: IPR Ibox, Index=118 This register contains various CPU instruction fetch/decode unit and branch unit (IDU) control and status information. | ||
| TST | <39>RW | Setting this bit asserts the test_status_h<1> signal. |
| ISTA | <38>RO | Reading this bit indicates Icache BIST status. If set, the BIST was successful. |
| Reserved | <37>RW,1 | Reserved to DIGITAL. Must be one. |
| FBD | <36>RW | If set, forces bad Icache data parity. MBZ in normal operation. |
| FBT | <35>RW | If set, forces bad Icache tag parity. MBZ in normal operation. |
| FMS | <34> | If set, forces misses on Icache references. MBZ in normal operation. |
| SLE | <33> | If set, enables serial line interrupts. |
| CRDE | <32> | If set, enables correctable error interrupts. |
| SDE | <30> | If set, enables the PAL shadow registers. |
| SPE<1:0> | <29:28> | If SPE<1> is set, it enables super-page mapping of I-stream virtual address VA<39:13> directly to physical PA<39:13>. If SPE<0> is set (NT mode), it enables super-page mapping of Istream virtual addresses VA<42:30> = 1FFE directly to physical address PA<39:30> = 0. VA<30:13> is mapped directly to PA<30:13>. |
| HWE | <27>RW | If set, allows PALRES instructions to be issued in kernel mode. |
| FPE | <26>RW | If set, floating point instructions may be issued. |
| TMD | <25>RW | If set, disables the IDU timeout counter. |
| TMM | <24>RW | If set, the timeout counter counts 5,000 cycles before asserting timeout reset. If clear, the counter counts 1 billion cycles before asserting timeout reset. |
| IMSK<3:0> | <23:20>RW | If set, each IMSK<3:0> signal disables the corresponding irq_h<3:0> interrupt. |
| Reserved | <18> | Test mode bit, must be zero. |
| BSE | <17> | If set, enables support for byte and word data structures. |
| PME<1:0> | <09:08> | Performance counter master enable bits. If both <1> and <0> are clear, all performance counters in the PMCTR IPR are disabled. If either bit is set, the counter is enabled according to the settings of the PMCTR CTL fields. |